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November 2000
NS ESIG E W D E NT R N CE M D FO A r at NDE D RE P L ente MM E N D E ort C om/tsc O RE C Supp ME l.c NOT RECOM chnical .intersi 14-Bit/16-Bit, Microprocessorww Te NO ur rw act o ERSIL o Compatible, 2-Chip, A/D Converter cont -INT 8 1-88
(R)
ICL7104
Features
* 16-Bit/14-Bit Binary Three-State Latched Outputs Plus Polarity and Overrange * Ideally Suited for Interface to UARTs and Microprocessors * Conversion on Demand or Continuously * Guaranteed Zero Reading for 0V Input * True Polarity at Zero Count for Precise Null Detection * Single Reference Voltage for True Ratiometric Operation * Onboard Clock and Reference * Auto-Zero, Auto-Polarity * Accuracy Guaranteed to 1 Count * All Outputs TTL Compatible * 4V Analog Input Range * Status Signal Available for External Sync, A/Z in Preamp, Etc.
Description
The ICL7104, combined with the ICL8052 or ICL8068, forms a member of Intersil' high performance A/D converter family. The ICL7104-16, performs the analog switching and digital function for a 16-bit binary A/D converter, with full three-state output, UART handshake capability, and other outputs for easy interfacing. The ICL7014-14 is a 14-bit version. The analog section, as with all Intersil' integrating converters, provides fully precise Auto-Zero, Auto-Polarity (including 0 null indication), single reference operation, very high input impedance, true input integration over a constant period for maximum EMI rejection, fully rationmetric operation, over-range indication, and a medium quality built-in reference. The chip pair also offers optional input buffer gain for high sensitivity applications, a built-in clock oscillator, and output signals for providing an external Auto-Zero capability in preconditioning circuitry, synchronizing external multiplexers, etc.
Part Number Information
PART NUMBER ICL7104-14CPL LCL7104-16CPL TEMP. RANGE ( oC) 0 to 70 0 to 70 PACKAGE 40 Ld PDIP 40 Ld PDIP PKG. NO. E40.6 E40.6
Pinouts
ICL7104 (PDIP) TOP VIEW
ICL7104-16 V++ DIG GND STTS POL OR BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 ICL7104-14 V++ 1 DIG GND STTS POL OR BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 NC NC BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 2 3 4 5 6 7 8 9 10 ICL7104-14 40 V39 COMP IN 38 REFCAP 1 37 VREF 36 AZ 35 ANALOG GND 34 REFCAP 2 33 BUF IN 32 ANALOG I/P ICL7104-16
31 V+ ICL7104-14 (OUTLINE DWGS DL, 11 30 CE/LD JL, PL) 12 29 SEN 13 14 15 16 17 18 19 20 28 R/H 27 MODE 26 CLK 2 25 CLK 1 24 CLK 3 23 HBEN 22 LBEN 21 BIT 1 HBEN MBEN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
File Number
3091.2
1
ICL7104 Functional Block Diagram
+15V -15V -BUF IN REF OUT 6 8 7 1 10 BUFFER A1 + +BUF IN 13 RINT BUF OUT 9 CINT -INT IN 11 INTEG. A2 + -1.2V +INT IN 12 CAZ +BUF IN 33 SW3 VREF ANALOG INPUT ANALOG GND 37 SW5 SW6 32 35 38 REF CAP (1) CREF 34 REF CAP (2) SW4 SW7 SW9 1 +15V 31 +5V 2 40 25 26 3 SW8 SW2 SW1 AZ 36 COMP IN 300k 39 7104 ZERO CROSSING DETECTOR CONTROL LOGIC 29 SEN 27 MODE 28 R/H INT OUT 14 COMP. A3 + COMP OUT +5V 2 50k -15V COUNTER LATCHES BITS OR POL 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 5 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 THREE-STATE OUTPUTS 24 HBEN 23 MBEN 22 LBEN 30 CE/LD
INT. 3 REF. 300pF 5k 10k 5 10F
-
-
-
8052/8068
-15V CLOCK CLOCK STTS (1) (2)
FIGURE 1. ICL8052A (8068A)/ICL7104 16-BIT/14-BIT A/D CONVERTER FUNCTIONAL DIAGRAM
Pin Descriptions
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SYMBOL V++ GND STTS POL OR BIT 16 BIT 14 BIT 15 BIT 13 BIT 14 BIT 12 BIT 13 BIT 11 BIT 12 BIT 10 BIT 11 BIT 9 BIT 10 NC BIT 9 NC BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 -16 -14 -16 -14 -16 -14 -16 -14 -16 -14 -16 -14 -16 -14 -16 -14 OPTION Digital Ground: 0V, ground return. Status Output: HI during integrate and deintegrate until data is latched. LO when analog section is in auto-zero configuration. Polarity: Three-state output. HI for positive input. Over Range: Three-state output. Most Significant Bit (MSB). DATA Bits: Three-state outputs. See Table 3 for format of ENABLES and bytes. HIGH = true. DESCRIPTION Positive Supply Voltage: Nominally +15V.
2
ICL7104 Pin Descriptions
PIN NO. 21 22 SYMBOL BIT 1 LBEN (Continued) OPTION Least Significant Bit (LSB). LOW BYTE ENABLE: If not in handshake mode (see pin 27) when LO (with CE/LD, pin 30) activates low-order byte outputs, BITS 1-8. When in handshake mode (see pin 27), serves as a low byte flag output. See Figures 11, 12, 13. -16 -14 -16 -14 MID BYTE ENABLE: Activates Bits 9-16, see LBEN (pin 22) HIGH BYTE ENABLE: Activates Bits 9-14, POL, OR, see LBEN (pin 22) HIGH BYTE ENABLE: Activates POL, OR, see LBEN (pin 22). RC oscillator pin: Can be used as clock output. Clock Input: External clock or ocsillator. Clock Output: Crystal or RC oscillator. INPUT LO: Direct output mode where CE/LD, HBEN, MBEN and LBEN act as inputs directly controlling byte outputs. If pulsed HI causes immediate entry into handshake mode (see Figure 13). If HI, enables CE/LD, HBEN, MBEN and LBEN as outputs. Handshake mode will be entered and data output as in Figures 11 and 12 at conversion completion. RUN/HOLD: Input HI conversions continuously performed every 217(-16) or 215(-14) clock pulses. Input LO conversion in progress completed, converter will stop in Auto-Zero 7 counts before input integrate. SEND ENABLE: Input controls timing of byte transmission in handshake mode. HI indicates `send'. CHIP ENABLE/ LOAD: WITH MODE (PIN 27) LO, CE/LD serves as a master output enable; when HI, the bit outputs and POL, OR are disabled. With MODE HI, pin serves as a LOAD strobe (-ve going) used in handshake mode. See Figures 11 and 12. Positive Logic Supply Voltage: Nominally +5V. Analog Input: High Side. Buffer Input: Buffer Analog to analog chip (ICL8052 or ICL8086). Reference Capacitor: Negative Side. Analog Ground: Input low side and reference low side. Auto-Zero node. Voltage Reference: Input (positive side). Reference Capacitor: Positive side. Comparator Input: From 8052/8068. Negative Supply Voltage: Nominally -15V. DESCRIPTION
23 24 25 26 27
MBEN HBEN HBEN CLOCK3 CLOCK 1 CLOCK 2 MODE
28
R/H
29 30
SEN CE/LD
31 32 33 34 35 36 37 38 39 40
V+ AN I/P BUF IN REFCAP2 AN. GND A-Z VREF REFCAP1 COMP-IN V-
3
ICL7104
Absolute Maximum Ratings
V+ Supply (GND to V+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V V++ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32V Positive Supply Voltage (GND to V++). . . . . . . . . . . . . . . . . . . . 17V Negative Supply Voltage (GND to V-) . . . . . . . . . . . . . . . . . . . . -17V Analog Input Voltage (Pins 32 - 39)(Note 4). . . . . . . . . . . . V++ to VDigital Input Voltage (Pins 2 - 30) (Note 5) . . . . . . . . . . . . (GND - 0.3V) to (V+ + 0.3V)
Thermal Information
Thermal Resistance (Typical, Note 1) JA ( oC/W) 40 Ld PDIP Package . . . . . . . . . . . . . . 60 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. For supply voltages less than 15V, the absolute maximum input voltage is equal to the supply voltage. 3. Short circuit may be to ground or either supply. Rating applies to 70oC ambient temperature. 4. Input voltages may exceed the supply voltages provided the input current is limited to 100A. 5. Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device latchup. For this reason it is recommended that the power supply to the ICL7104 be established before any inputs from sources not on that supply are applied.
ICL7104 Electrical Specifications V+ = +5V, V++ = +15V, V- = -15V, TA = 25oC, fCLOCK = 200kHz
PARAMETER Clock Input, CLK 1 Comparator I/P, COMP IN (Note 6) Inputs with Pulldown, MODE Inputs with Pullups SEN, R/H LBEN, MBEN, HBEN, CE/LD (Note 7) Input High Voltage, All Digital Inputs Input Low Voltage, All Digital Inputs Digital Outputs Three-Stated On, LBEN, MBEN (16 Only), HBEN, CE/LD BIT n, POL, OR (Note 8) Digital Outputs Three-Stated Off Bit n, POL, OR Non Three-State Digital Output STTS Clock 2 Clock 3 (-14 Only) Switch Switch 1 Switches 2, 3 Switches 4, 5, 6, 7, 8, 9 Switch Leakage Clock Frequency (Note 9) Supply Currents +5V Supply Current All outputs high impedance +5V Supply Current -5V Supply Current SYMBOL IIN IIN IIH IIL IIH IIL VIH V IL VOL VOH VOH IOL IOL = 1.6mA IOH = -10A IOH = -240A 0 VOUT V+ TEST CONDITIONS VIN = +5V to 0V VIN = 0V to +5V VIN = +5V VIN = 0V VIN = +5V VIN = 0V MIN 2 -10 1 -10 -10 -30 2.5 2.4 -10 TYP 7 0.001 5 0.01 0.01 -5 2.0 1.5 0.27 4.5 3.5 0.001 MAX 30 10 30 10 10 -1 1.0 0.4 +10 UNITS A A A A A A V V V V V A
VOL VOH VOL VOH VOL VOH rDS(ON) rDS(ON) rDS(ON) ID(OFF) fCLOCK I+ I++ I-
IOL = 3.2mA IOH = -400A IOL= 320A IOH = -320A IOL = 1.6mA IOH = -320A
2.4 2.4 DC
0.3 3.3 0.5 4.5 0.27 3.5 25k 4k 2k 15 200 200 0.3 25
0.4 0.4 20k 10k 400 600 1.0 200
V V V V V V pA kHz A mA A
Frequency = 200kHz Frequency = 200kHz Frequency = 200kHz
-
4
ICL7104
ICL7104 Electrical Specifications V+ = +5V, V++ = +15V, V- = -15V, TA = 25oC, fCLOCK = 200kHz (Continued)
PARAMETER Supply Voltage Range Logic Supply Positive Supply Negative Supply NOTES: 6. This specification applies when not in Auto-Zero phase. 7. Apply only when these pins are inputs, i.e., the mode pin is low, and the 7104 is not in handshake mode. 8. Apply only when these pins are outputs, i.e., the mode pin is high, or the 7104 is in handshake mode. 9. Clock circuit shown in Figures 14 and 15. 10. V+ must not be more positive than V++. SYMBOL V+ V++ VTEST CONDITIONS Note 10 MIN 4 10 -16 TYP MAX 11 16 -10 UNITS V V V
System Electrical Specifications: ICL8068/ICL7104 V++ = +15V, V+ = +5V, V- = -15V, fCLOCK = 200kHz (Note 16)
PARAMETER Zero Input Reading Ratiometric Error (Note 13) Linearity Over Full Scale (Error of Reading from Best Straight Line) Differential Linearity (Difference between Worst Case Step of Adjacent Counts and Ideal Step) Rollover Error (Difference in Reading for Equal Positive & Negative Voltage Near Full Scale) Noise (P-P Value Not Exceeded 95% of Time) Leakage Current at Input (Note 14) Zero Reading Drift Scale Factor Temperature Coefficient (Note 15) TEST CONDITIONS VIN = 0V, VREF = 2V VIN = VREF = 2V -4V VIN +4V -4V VIN +4V ICL8068A/ICL7104-14 MIN -00000 -1 TYP 00000 0 0.5 0.01 MAX +00000 1 1 ICL8068A/ICL7104-16 MIN -00000 -1 TYP 00000 0 0.5 0.01 MAX +00000 1 1 UNITS Counts LSB LSB LSB
-VIN = +VIN 4V
-
0.5
1
-
0.5
1
LSB
VIN = 0V, Full Scale = 4V VIN = 0V VIN = 0V, 0oC to 70oC VIN = 4V, 0oC to 50oC ext. ref. 0ppm/oC
-
2 100 0.5 2
165 5
-
2 100 0.5 2
165 5
V pA V/oC ppm/oC
System Electrical Specifications: ICL8052/ICL7104 V++ = +15V, V+ = +5V, V- = -15V, fCLOCK = 200kHz
(Note 16) TEST CONDITIONS VIN = 0V, VREF = 2V VIN = VREF = 2V -4V VIN +4V -4V VIN +4V ICL8052A/ICL7104-14 MIN -00000 -1 TYP 00000 0 0.5 0.01 MAX +00000 1 1 ICL8052A/ICL7104-16 MIN -00000 -1 TYP 00000 0 0.5 0.01 MAX +00000 1 1 UNITS Counts LSB LSB LSB
PARAMETER Zero Input Reading Ratiometric Error (Note 15) Linearity Over Full Scale (Error of Reading from Best Straight Line) Differential Linearity (Difference between Worst Case Step of Adjacent Counts and Ideal Step) Rollover Error (Difference in Reading for Equal Positive and Negative Voltage Near Full Scale) Noise (Peak-to-Peak Value Not Exceeded 95% of Time)
-VIN = +VIN 4V
-
0.5
1
-
0.5
1
LSB
VIN = 0V, Full Scale = 4V
-
30
-
-
30
-
V
5
ICL7104
System Electrical Specifications: ICL8052/ICL7104 V++ = +15V, V+ = +5V, V- = -15V, fCLOCK = 200kHz
(Note 16) (Continued) TEST CONDITIONS VIN = 0V VIN = 0V, 0oC to 70oC VIN = 4V, 0oC to 50oC ext. ref. 0ppm/oC ICL8052A/ICL7104-14 MIN TYP 20 0.5 2 MAX 30 ICL8052A/ICL7104-16 MIN TYP 20 0.5 2 MAX 30 UNITS pA V/oC ppm/oC
PARAMETER Leakage Current at Input (Note 14) Zero Reading Drift Scale Factor Temperature Coefficient
NOTES: 11. Tested with low dielectric absorption integrating capacitor. 12. The input bias currents are junction leakage currents which approximately double for every 10oC increase in the junction temperature, TJ . Due to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. TJ = TA + RJAPD where RJA is the thermal resistance from junction to ambient. A heat sink can be used to reduce temperature rise. 13. The temperature range can be extended to 70oC and beyond if the Auto-Zero and Reference capacitors are increased to absorb the high temperature leakage of the 8068. See note 14 above.
14. System Electrical Specifications are not tested; for reference only.
CONTROL CONVERT
MODE
R/H OR POL 7104 -16 MSB 18 18
8052A/ 8068A
LSB CE/LD HBEN MBEN LBEN OR CHIP SELECT 2 CHIP SELECT 1
FIGURE 2. FULL 18-BIT THREE-STATE OUTPUT
CONVERT
CONVERT
CONVERT
MODE CE/LD
R/H OR POL MSB 2
MODE CE/LD
R/H OR POL MSB 8052A/ 8068A 16 2
MODE CE/LD
R/H OR POL MSB 10
8052A/ 8068A
7104
8
8052A/ 8068A
7104
7104
LSB HBEN MBEN LBEN
8
LSB HBEN MBEN LBEN
LSB HBEN MBEN LBEN
8
CONTROL
CONTROL
CONTROL
FIGURE 3. VARIOUS COMBINATIONS OF BYTE DISABLES
6
ICL7104
tCEA CE/LD AS INPUT HBEN AS INPUT MBEN AS INPUT LBEN AS INPUT tDAB HIGH BYTE DATA MIDDLE BYTE ENABLE LOW BYTE ENABLE = HIGH IMPEDANCE DATA VALID DATA VALID tDHB tDAC DATA VALID DATA VALID DATA VALID tDHC tBEA
FIGURE 4. DIRECT MODE TIMING DIAGRAM TABLE 1. DIRECT MODE TIMING REQUIREMENTS (Note: Not tested in production) SYMBOL tBEA tDAB tDHB tCEA tDAC tDHC tCWH DESCRIPTION XBEN (Min) Pulse Width. Data Access Time from XBEN. Data Hold Time from XBEN. CE/LD Min. Pulse Width. Data Access Time from CE/LD. Data Hold Time from CE/LD. CLOCK 1 High Time. MIN TYP 300 300 200 350 350 280 1000 MAX UNIT ns ns ns ns ns ns ns
TABLE 2. HANDSHAKE TIMING REQUIREMENTS (Note: Not tested in production) SYMBOL tMW tSM tME tMB tCEL tCEH tCBL tCBH tCDH tCDL tSS tCBZ tCEZ tCWH Mode Pulse (Min). Mode Pin Set-Up Time. Mode Pin High to Low Z CE/LD High Delay. Mode Pin High to XBEN Low Z (High) Delay. Clock 1 High to CE/LD Low Delay. Clock 1 High to CE/LD High Delay. Clock 1 High to XBEN Low Delay. Clock 1 High to XBEN High Delay. Clock 1 High to Data Enabled Delay. Clock 1 Low to Data Disabled Delay. Send ENABLE Set-Up Time. Clock 1 High to XBEN Disabled Delay. Clock 1 High to CE/LD Disabled Delay. Clock 1 High Time. DESCRIPTION MIN 1250 TYP 20 -150 200 200 700 600 900 700 1100 1100 -350 2000 2000 1000 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns
7
ICL7104
CLOCK 1 H (PIN 25) L EITHER: H MODE PIN L OR INTERNAL LATCH PULSE IF MODE "HI" INTERNAL UART MODE NORM CE/LD SEN (EXTERNAL SIGNAL) HBEN H L H DON'T CARE L H L tCWH tMW DON'T CARE STABLE tSM
IGNORED tCEL tME EXT tCEH EXT tSS
IGNORED
tCEZ DON'T CARE
tMB tCBL DATA VALID, STABLE tCDH tCDL tCBH tCBZ
O/R, POL H 01-14 L LBEN H L
BITS 1-5 HANDSHAKE MODE TRIGGERED BY OR
DATA VALID, STABLE THREE-STATE -16 HAS EXTRA (MBEN) PHASE THREE-STATE WITH PULLUP
FIGURE 5. HANDSHAKE MODE TIMING DIAGRAM
Detailed Description
ANALOG SECTION Figure 6 shows the equivalent Circuit of the Analog Section of both the ICL7104/8052 and the ICL7104/8068 in the 3 different phases of operation. If the Run/Hold pin is left open or tied to V+, the system will perform conversions at a rate determined by the clock frequency: 131,072 for - 16 and 32,368 for - 14 clock periods per cycle (see Figure 8 conversion timing). Auto-Zero Phase I (Figure 6A) During Auto-Zero, the input of the buffer is shorted to analog ground thru switch 2, and switch 1 closes a loop around the integrator and comparator. The purpose of the loop is to charge the Auto-Zero capacitor until the integrator output no longer changes with time. Also, switches 4 and 9 recharge the reference capacitor to VREF . Input Integrate Phase II (Figure 6B) During input integrate the Auto-Zero loop is opened and the analog input is connected to the buffer input thru switch 3. (The reference capacitor is still being charged to V REF during this time.) If the input signal is zero, the buffer, integrator and comparator will see the same voltage that existed in the previous sate (Auto-Zero). Thus the integrator output will not change but will remain stationary during the entire Input Integrate cycle. If VIN is not equal to zero, an unbalanced condition exists compared to the Auto-Zero phase, and the integrator will generate a ramp whose slope is proportional to VIN . At the end of this phase, the sign of the ramp is latched into the polarity F/F. Deintegrate Phase III (Figures 6C and 6D) During the Deintegrate phase, the switch drive logic uses the output of the polarity F/F in determining whether to close switches 6 and 9 or 7 and 8. If the input signal was positive, switches 7 and 8 are closed and a voltage which is V REF more negative than during Auto-Zero is impressed on the buffer input. Negative inputs will cause +VREF to be applied to the buffer input via switches 6 and 9. Thus, the reference capacitor generates the equivalent of a (+) reference or a (-) reference from the single reference voltage with negligible error. The reference voltage returns the output of the integrator to the zero-crossing point established in Phase I. The time, or number of counts, required to do this is proportional to the input voltage. Since the Deintegrate phase can be twice as long as the Input integrate phase, the input voltage required to give a full scale reading = 2VREF .
NOTE: Once a zero crossing is detected, the system automatically reverts to Auto-Zero phase for the leftover Deintegrate time (unless RUN/HOLD is manipulated, see RUN/HOLD input in detailed description, digital section).
8
ICL7104
RINT AN I/P 3 BUFFER A1 + 8 9 6 7 1 POL 2 CAZ CINT INTEGRATOR A2 +
-
-
COMP. A3 +
-
ZERO CROSS. DET.
D ZERO CROSSING F/F CL CL
Q
-
+ 4
CREF
VREF
FIGURE 6A. PHASE I AUTO-ZERO
RINT AN I/P 3 BUFFER A1 + 8 9 6 7 1 POL 2 CAZ CINT INTEGRATOR A2 +
D COMP. A3 +
POL F/F CL
Q
POL
-
-
PHASE II ZERO CROSS. DET. D ZERO CROSSING F/F CL CL Q
-
-
+ 4
CREF
VREF
FIGURE 6B. PHASE II INTEGRATE INPUT
RINT +AN I/P 3 BUFFER A1 + 8 9 6 7 1 POL 2 CAZ CINT INTEGRATOR A2 +
-
-
COMP. A3 +
-
ZERO CROSS. DET.
D
Q ZERO CROSSING F/F CL CL
-
+ 4
CREF
VREF
FIGURE 6C. PHASE III + DEINTEGRATE
9
ICL7104
RINT -AN I/P 3 BUFFER A1 + 8 9 6 7 1 POL 2 CAZ CINT INTEGRATOR A2 +
-
-
COMP. A3 +
-
ZERO CROSS. DET.
D
Q ZERO CROSSING F/F CL CL
-
+ 4
CREF
VREF
FIGURE 6D. PHASE III DEINTEGRATE TABLE 3. THREE-STATE BYTE FORMATS AND ENABLE PINS CE/LD HBEN ICL7104-16 POL O/R B16 B15 B14 MBEN B13 B12 B11 B10 B9 B8 B7 B6 LBEN B5 B4 B3 B2 B1
HBEN ICL7104-14 POL O/R B14 B13 B12 B11 B10 B9 B8 B7 B6
LBEN B5 B4 B3 B2 B1
TABLE 4. TYPICAL COMPONENT VALUES (V++ = +15V, V+ = 5V, V- = 5V, V- = -15V, fCLOCK = 200kHz) ICL8052/8068 WITH Full scale VIN Buffer Gain RINT CINT CAZ CREF VREF Resolution 200 10 100 0.33 1 10 100 3.1 ICL7104-16 800 1 43 0.33 1 1 400 12 4000 1 200 0.33 1 1 2000 61 100 10 47 0.1 1 10 50 6.1 ICL7104-14 4000 1 180 0.1 1 1 2000 244 UNIT mV V/V k F F F mV V
Buffer Gain At the end of the auto-zero interval, the instantaneous noise voltage on the auto-zero capacitor is stored, and subtracts from the input voltage while adding to the reference voltage during the next cycle. The result is that this noise voltage effectively is somewhat greater than the input noise voltage of the buffer itself during integration. By introducing some voltage gain into the buffer, the effect of the auto-zero noise (referred to the input) can be reduced to the level of the inherent buffer noise. This generally occurs with a buffer gain of between 3 and 10. Further increase in buffer gain merely increases the total offset to be handled by the auto-zero loop, and reduces the available buffer and integrator swings, without improving the noise performance of the system. The circuit recommended for doing this with the ICL8068/ICL7104 is shown in Figure 7. With careful layout, the circuit shown can achieve effective input noise voltages on the order of 1 to 2V, allowing full 16-bit use with full scale inputs of a low as 150mV. Note that at this level, thermoelectric EMFs between PC boards, IC pins, etc., due to local temperature changes can be very troublesome. For further discussion, see Application Note AN030.
ICL8052 vs ICL8068 The ICL8052 offers significantly lower input leakage currents than the ICL8068, and may be found preferable in systems with high input impedances. However, the ICL8068 has substantially lower noise voltage, and for systems where system noise is a limiting factor, particularly in low signal level conditions, will give better performance.
Component Value Selection
For optimum performance of the analog section, care must be taken in the selection of values for the integrator capacitor and resistor, auto-zero capacitor, reference voltage, and conversion rate. These values must be chosen to suit the particular application.
10
ICL7104
10-50K +15V -15V 100k RINT BUF OUT 9 CINT -INT IN 11 INTEG. A2 + -1.2V INT OUT 14 COMP. A3 + COMP OUT +5V 2 -15V
-BUF IN
REF OUT 300pF 5k 10k 5 6 8 7 1 INT. 3 REF. 10 BUFFER A1 + +BUF IN 13
-
-
-
8068
+INT IN 12
TO ICL7104
FIGURE 7. ADDING BUFFER GAIN TO ICL8068 COUNTS PHASE I -16 -14 32768 8192
POLARITY DETECTED
PHASE II 32768 8192
PHASE III 65536 16384
ZERO CROSSING OCCURS ZERO CROSSING DETECTED
INTEGRATOR OUTPUT AZ PHASE I INTERNAL CLOCK INTERNAL LATCH STATUS OUTPUT
INT PHASE II
DEINT PHASE III
AZ
NUMBER OF COUNTS TO ZERO CROSSING PROPORTIONAL TO VIN
AFTER ZERO CROSSING, ANALOG SECTION WILL BE IN AUTOZERO CONFIGURATION
FIGURE 8. CONVERSION TIMING
Integrating Resistor The integrating resistor is determined by the full scale input voltage and the output current of the buffer used to charge the integrator capacitor. This current should be small compared to the output short circuit current such that thermal effects are kept to a minimum and linearity is not affected. Values of 5 to 40A give good results with a nominal of 20A. The exact value may be chosen by:
full scale voltage (see note) R I NT = -----------------------------------------------------------------------20A NOTE: If gain is used in the buffer amplifier then ( Bu fferGa in ) (full scale voltage) R IN T = --------------------------------------------------------------------------------------20A
to give 9 volt swing for full scale inputs. This is a compromise between possibly saturating the integrator (at +14 volts) due to tolerance build-up between the resistor, capacitor and clock and the errors a lower voltage swing could induce due to offsets referred to the output of the comparator. In general, the value of CINT is given by:
(32768 for - 16) x 20A x clock period (8192 for -14) C I NT = --------------------------------------------------------------------------------------------------------Integrator Output Voltage Swing

A very important characteristic of the integrating capacitor is that it have low dielectric absorption to prevent roll-over or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to the reference. This ratiometric condition should read half scale (100...000) and any deviation is probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in less critical applications.
Integrating Capacitor The product of integrating resistor and capacitor is selected
11
ICL7104
Auto-Zero and Reference Capacitor The size of the auto-zero capacitor has some influence on the noise of the system, a large capacitor giving less noise. The reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible.
NOTE: When gain is used in the buffer amplifier the reference capacitor should be substantially larger than the auto-zero capacitor. As a rule of thumb, the reference capacitor should be approximately the gain times the value of the auto-zero capacitor. The dielectric absorption of the reference cap and auto-zero cap are only important at power-on or when the circuit is recovering from an overload. Thus, smaller or cheaper caps can be used here if accurate readings are not required for the first few seconds of recovery.
and control logic and UART handshake logic, as shown in the Block Diagram Figure 9 (16-bit version shown). Throughout this description, logic levels will be referred to as "low" or "high". The actual logic levels are defined under "ICL7104 Electrical Specification". For minimum power consumption, all inputs should swing from GND (low) to V+ (high). Inputs driven from TTL gates should have 3 - 5k pullup resistors added for maximum noise immunity. MODE Input The MODE input is used to control the output mode of the converter. When the MODE pin is connected to GND or left open (this input is provided with a pulldown resistor to ensure a low level when the pin is left open), the converter is in its "Direct" output mode, where the output data is directly accessible under the control of the chip and byte enable inputs. When the MODE input is pulsed high, the converter enters the UART handshake mode and outputs the data in three bytes for the 7104-16 or two bytes for the 7104-14 then returns to "direct" mode. When the MODE input is left high, the converter will output data in the handshake mode at the end of every conversion cycle. (See section entitled "Handshake Mode" for further details). STATUS Output During a conversion cycle, the STATUS output goes high at the beginning of Input Integrate (Phase II), and goes low one-half clock period after new data from the conversion has been stored in the output latches. See Figure 8 for details of this timing. This signal may be used as a "data valid" flag (data never changes while STATUS is low) to drive interrupts, or for monitoring the status of the converter.
Reference Voltage The analog input required to generate a full scale output is VIN = 2VREF . The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. The resolution of the ICL7104 at 16 bits is one part in 65536, or 15.26ppm. Thus, if the reference has a temperature coefficient of 50ppm/C (on board reference) a temperature change of 1/3C will introduce a one-bit absolute error. For this reason, it is recommended that an external high quality reference be used where the ambient temperature is not controlled or where high-accuracy absolute measurements are being made.
Detailed Description
DIGITAL SECTION The digital section includes the clock oscillator circuit, a 16-bit or 14-bit binary counter with output latches and TTLcompatible three-state output drivers, polarity, over-range
TABLE 5. THREE-STATE BYTE FORMATS AND ENABLE PINS CE/LD HBEN ICL7104-16 POL O/R B16 B15 B14 MBEN B13 B12 B11 B10 B9 B8 B7 B6 LBEN B5 B4 B3 B2 B1
HBEN ICL7104-14 POL O/R B14 B13 B12 B11 B10 B9 B8 B7 B6
LBEN B5 B4 B3 B2 B1
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ICL7104
18/16 THREE-STATE OUTPUTS
HBEN
18/16 LATCHES INITIAL CLEAR
MBEN (-16 ONLY)
18/16 BIT COUNTER LATCH CLOCK LBEN
TO ANALOG SECTION
COMP OUT AZ INT DEINT(+) DEINT(-)
CONVERSION CONTROL LOGIC 2 STATUS 26 R/H
OSCILLATOR AND CLOCK CIRCUITRY 24 23 25
HANDSHAKE LOGIC 21 MODE 27 SEND
CE/LD
CLOCK CLOCK CLOCK (2) (3) (1)
FIGURE 9. DIGITAL SECTION
OPTION MIN DEINT TERMINATED AT ZERO CROSSING DETECTION MAX -14 7161 8185 -16 28665 32761 STATIC IN HOLD STATE INT PHASE 7 COUNTS INTERNAL CLOCK INTERNAL LATCH STATUS OUTPUT RUN/HOLD INPUT
INTEGRATOR OUTPUT
FIGURE 10. RUN/HOLD OPERATION
Run/Hold Input When the Run/Hold input is connected to V+ or left open (this input has pullup resistor to ensure a high level when the pin is left open), the circuit will continuously perform conversion cycles, updating the output latches at the end of every Deintegrate (Phase III) portion of the conversion cycle (See Figure 8). (See under "Handshake Mode" for exception.) In this mode of operation, the conversion cycle will be performed in 131,072 for 7104-16 and 32768 for 7104-14 clock periods, regardless of the resulting value. If Run/Hold goes low at any time during Deintegrate (Phase III) after the zero crossing has occurred, the circuit will immediately terminate Deintegrate and jump to Auto-Zero. This feature can be used to eliminate the time spent in Deintegrate after the zero-crossing. If Run/Hold stays or goes low, the converter will ensure a minimum Auto-Zero time, and then wait in Auto-Zero until the Run/Hold input goes high. The converter will begin the Integrate (Phase II) portion of the next conversion (and the STATUS output will go high) seven clock periods after the high level is detected
at Run/Hold. See Figure 10 for details. Using the Run/Hold input in this manner allows an easy "convert on demand" interface to be used. The converter may be held at idle in Auto-Zero with Run/Hold low. When Run/Hold goes high the conversion is started, and when the STATUS output goes low the new data is valid (or transferred) to the UART - see Handshake Mode). Run/Hold may now go low terminating Deintegrate and ensuring a minimum Auto-Zero time before stopping to wait for the next conversion. Alternately, Run/Hold can be used to minimize conversion time by ensuring that it goes low during Deintegrate, after zero crossing, and goes high after the hold point is reached. The required activity on the Run/Hold input can be provided by connecting it to the CLOCK3 (-14), CLOCK2 (-16) Output. In this mode the conversion time is dependent on the input value measured. Also refer to Intersil Application Bulletin A030 for a discussion of the effects this will have on Auto-Zero performance. If the Run/Hold input goes low and stays low during AutoZero (Phase I), the converter will simply stop at the end of
13
ICL7104
the Auto-Zero and wait for Run/Hold to go high. As above, Integrate (Phase II) begins seven clock periods after the high level is detected. Direct Mode When the MODE pin is left at a low level, the data outputs [bits 1 through 8 low order byte, See Table 3 for format of middle (-16) and high order bytes] are accessible under control of the byte and CHIP ENABLE terminals as inputs. These ENABLE inputs are all active low, and are provided with pullup resistors to ensure an inactive high level when left open. When the CHIP ENABLE input is low, taking a byte ENABLE input low will allow the outputs of that byte to become active (three-stated on). This allows a variety of parallel data accessing techniques to be used. The timing requirements for these outputs are shown under AC Specifications and Table 1. It should be noted that these control inputs are asynchronous with respect to the converter clock - the data may be accessed at any time. Thus it is possible to access the data while it is being updated, which could lead to scrambled data. Synchronizing the access of data with the conversion cycle by monitoring the STATUS output will prevent this. Data is never updated while STATUS is low. Also note the potential bus conflict described under "Initial Clear Circuitry". Handshake Mode The handshake output mode is provided as an alternative means of interfacing the ICL7104 to digital systems, where the A/D converter becomes active in controlling the flow of data instead of passively responding to chip and byte ENABLE inputs. This mode is specifically designed to allow a direct interface between the ICL7104 and industry-standard UARTs (such as the Intersil CMOS UARTs, IM6402/3) with no external logic required. When triggered into the handshake mode, the ICL7104 provides all the control and flag signals necessary to sequence the three (ICL7106-16) or two (ICL7104-14) bytes of data into the UART and initiate their transmission in serial form. This greatly eases the task and reduces the cost of designing remote data acquisition stations using serial data transmission to minimize the number of lines to the central controlling processor. Entry into the handshake mode will occur if either of two conditions are fulfilled; first, if new data is latched (i.e., a conversion is completed) while MODE pin (pin 27) is high, in which case entry occurs at the end of the latch cycle; or secondly, if the MODE pin goes from low to high, when entry will occur immediately (if new data is being latched, entry is delayed to the end of the latch cycle). While in the handshake mode, data latching is inhibited, and the MODE pin is ignored. (Note that conversion cycles will continue in the normal manner). This allows versatile initiation of handshake operation without danger of false data generation; if the MODE pin is held high, every conversion (other than those completed during handshake operations) will start a new handshake operation, while if the MODE pin is pulsed high, handshake operations can be obtained "on demand." When the converter enters the handshake mode, or when the MODE input is high, the chip and byte ENABLE terminals become TTL-compatible outputs which provide the control signals for the output cycle. The Send ENABLE pin (SEN) (pin 29) is used as an indication of the ability of the external device to receive data. The condition of the line is sensed once every clock pulse, and if it is high, the next (or first) byte is enabled on the next rising CLOCK 1 (pin 25) clock edge, the corresponding byte ENABLE line goes low, and the CHIP ENABLE / LOAD pin (pin 30) (CE/LD) goes low for one full clock pulse only, returning high. On the next falling CLOCK 1 clock pulse edge, if SEN remains high, or after it goes high again, the byte output lines will be put in the high impedance state (or three-stated off). One half pulse later, the byte ENABLE pin will be cleared high, and (unless finished) the CE/LD and the next byte ENABLE pin will go low. This will continue until all three (2 in the case of the 14-bit device) bytes have been sent. The bytes are individually put into the low impedance state i.e.: three-stated on during most of the time that their byte ENABLE pin is (active) low. When receipt of the last byte has been acknowledged by a high SEN, the handshake mode will be cleared, re-enabling data latching from conversion, and recognizing the condition of the MODE pin again. The byte and CHIP ENABLE will be three-stated off, if MODE is low, but held by their (weak) pullups. These timing relationships are illustrated in Figures 11, 12, and 13, and Table 2. Figure 11 shows the sequence of the output cycle with SEN held high. The handshake mode (Internal MODE high) is entered after the data latch pulse (since MODE remains high the CE/LD, LBEN, MBEN and HBEN terminals are active as outputs). The high level at the SEN input is sensed on the same high to low internal clock edge. On the next to high internal clock edge, the CE/LD and the HBEN outputs assume a low level and the high-order byte (POL and OR, and except for -16, Bits 9 - 14) outputs are enabled. The CE/LD output remains low for one full internal clock period only, the data outputs remain active for 11/2 internal clock periods, and the high byte ENABLE remains low for two clock periods. Thus the CE/LD output low level or low to high edge may be used as a synchronizing signal to ensure valid data, and the byte ENABLE as an output may be used as a byte identification flag. With SEN remaining high the converter completes the output cycle using CE/LD, MBEN and LBEN while the remaining byte outputs (see Table 3) are activated. The handshake mode is terminated when all bytes are sent (3 for -16, 2 for -14). Figure 12 shows an output sequence where the SEN input is used to delay portions of the sequence, or handshake, to ensure correct data transfer. This timing diagram shows the relationships that occur using an industry-standard IM6402/3 CMOS UART to interface to serial data channels. In this interface, the SEN input to the ICL7104 is driven by the TBRE (Transmitter Buffer Register Empty) output of the UART, and the CE/LD terminal of the ICL7104 drives the TBRL (Transmitter Buffer Register Load) input to the UART. The data outputs are paralleled into the eight Transmitter Buffer Register inputs. Assuming the UART Transmitter Buffer Register is empty,
14
ICL7104
the SEN input will be high when the handshake mode is entered after new data is stored. The CE/LD and HBEN terminals will go low after SEN is sensed, and the high order byte outputs become active. When CE/LD goes high at the end of one clock period, the high order byte data is clocked into the UART Transmitter Buffer Register. The UART TBRE output will now go low, which halts the output cycle with the HBEN output low, and the high order byte outputs active. When the UART has transferred the data to the Transmitter Register and cleared the Transmitter Buffer Register, the TBRE returns high. On the next ICL7104 internal clock high to low edge, the high order byte outputs are disabled, and one-half internal clock later, the HBEN output returns high. At the same time, the CE/LD and MBEN (-16) or LBEN outputs go low, and the corresponding byte outputs become active. Similarly, when the CE/LD returns high at the end of one clock period, the enabled data is clocked into the UART Transmitter Buffer Register, and TBRE again goes low. When TBRE returns to a high it will be sensed on the next ICL7104 internal clock high to low edge, disabling the data outputs. For the 16-bit device, the sequence is repeated for
ZERO-CROSSING OCCURS INTEGRATOR OUTPUT INTERNAL CLOCK INTERNAL LATCH STATUS OUTPUT MODE INPUT INTERNAL MODE SEN INPUT CE/LOAD HBEN HIGH BYTE DATA LBEN LOW BYTE DATA LBEN LOW BYTE DATA MODE HIGH ACTIVATES CE/LD, HBEN, LBEN DON'T CARE THREE-STATE HIGH IMPEDANCE DATA VALID DATA VALID MODE LOW NOT IN HANDSHAKE MODE DISABLES OUTPUTS CE/LD, HBEN, MBEN, LBEN UART NORM SEN SENSED SEN SENSED TERMINATES UART MODE ZERO-CROSSING DETECTED FOR -16 MBEN SEQUENCE INSERTED HERE
LBEN. One-half internal clock later, the handshake mode will be cleared, and the chip and byte ENABLE terminals return high and stay active (as long as MODE stays high). With the MODE input remaining high as in these examples, the converter will output the results of every conversion except those completed during a handshake operation. By triggering the converter into handshake mode with a low to high edge on the MODE input, handshake output sequences may be performed on demand. Figure 13 shows a handshake output sequence triggered by such an edge. In addition, the SEN input is shown as being low when the converter enters handshake mode. In this case, the whole output sequence is controlled by the SEN input, and the sequence for the first (high order) byte is similar to the sequence for the other bytes. This diagram also shows the output sequence taking longer than a conversion cycle. Note that the converter still makes conversions, with the STATUS output and Run/Hold input functioning normally. The only difference is that new data will not be latched when in handshake mode, and is therefore lost.
DATA VALID THREE-STATE WITH PULLUP
FIGURE 11. HANDSHAKE WITH SEN HELD POSITIVE
15
ICL7104
ZERO-CROSSING OCCURS INTEGRATOR OUTPUT INTERNAL CLOCK INTERNAL LATCH STATUS OUTPUT MODE INPUT INTERNAL MODE SEN INPUT (UART TBRE) CE/LOAD (UART TBRL) HBEN HIGH BYTE DATA MBEN MIDDLE BYTE DATA LBEN LOW BYTE DATA DON'T CARE THREE-STATE HIGH IMPEDANCE DATA VALID DATA VALID ZERO-CROSSING DETECTED
UART NORM
DATA VALID
FIGURE 12. HANDSHAKE - TYPICAL UART INTERFACE TIMING
16
ICL7104
POSITIVE TRANSITION CAUSES ENTRY INTO UART MODE INTERNAL CLOCK INTERNAL LATCH STATUS OUTPUT MODE INPUT INTERNAL UART MODE NORM SEN INPUT CE/LOAD AS OUTPUT HBEN HIGH BYTE DATA MBEN MIDDLE BYTE DATA LBEN LOW BYTE DATA DON'T CARE THREE-STATE HIGH IMPEDANCE DATA VALID THREE-STATE WITH PULLUP DATA VALID ZERO-CROSSING OCCURS ZERO-CROSSING DETECTED LATCH PULSE INHIBITED IN UART MODE DEINT PHASE III STATUS OUTPUT UNAFFECTED BY UART MODE
DATA VALID
FIGURE 13. HANDSHAKE TRIGGERED BY MODE
Initial Clear Circuitry The internal logic of the 7104 is supplied by an internal regulator between V++ and Digital Ground. The regulator includes a low-voltage detector that will clear various registers. This is intended to ensure that on initial power-up, the control logic comes up in Auto-Zero, with the 2nd, 3rd, and 4th MSB bits cleared, and the "mode" F/F cleared (i.e., in "direct" mode). This, however, will also clear these registers if the supply voltage "glitches" to a low enough value. Additionally, if the supply voltage comes up too fast, this clear pulse may be too narrow for reliable clearing. In general, this is not a problem, but if the UART internal "MODE" F/F should come up set, the byte and chip ENABLE lines will become active outputs. In many systems this could lead to bus conflicts, especially in non-handshake systems. In any case, SEN should be high (held high for non-handshake systems) to ensure that the MODE F/F will be cleared as fast as possible (see Figure 11 for timing). For these and other reasons, adequate supply bypass is recommended. Oscillator The ICL7104-14 is provided with a versatile three terminal oscillator to generate the internal clock. The oscillator may be overdriven, or may be operated as an RC or crystal oscillator. Figure 14 shows the oscillator configured for RC operation. The internal clock will be of the same frequency and phase as the voltage on the CLOCK 3 pin. The resistor and capacitor should be connected as shown. The circuit will oscillate at a frequency given by f = 0.45/RC. A 50 - 100k resistor is recommended for useful ranges of frequency. For optimum 60Hz line rejection, the capacitor value should be chosen such that 32768 (-16), 8192 (-14) clock periods is close to an integral multiple of the 60Hz period.
25 CLOCK 1 CLOCK 2
26 R CLOCK 3
24
C
fOSC = 0.45/RC
NOTE: Clock 3 has the same output drive as the bit outputs. FIGURE 14. RC OSCILLATOR (ICL7104-14 ONLY)
As a result of pin count limitations, the ICL7104-16 has only CLOCK 1 and CLOCK 2 available, and cannot be used as an RC oscillator. The internal clock will correspond to the inverse of the signal on CLOCK 2. Figure 15 shows a crystal oscillator circuit, which can be used with both 7104 versions. If an external clock is to be used, it should be applied to CLOCK 1. This internal clock will correspond to the signal applied to this pin.
V+
25 CLOCK 1 CLOCK 2
26
CAPACITOR VALUE
CRYSTAL
DEPENDS ON CRYSTAL TYP 0-30pF
FIGURE 15. CRYSTAL OSCILLATOR
17
ICL7104 Power Supply Sequencing
Because of the nature of the CMOS process used to fabricate the ICL7104, and the multiple power supplies used, there are certain conditions of these supplies under which a disabling and potentially damaging SCR action can occur. All of these conditions involve the V+ supply (Norm +5V) being more positive than the V++ supply. If there is any possibility of this occurring during start-up, shut down, under transient conditions during operation, or when inserting a PC board into a "hot" socket, etc., a diode should be placed between V+ and V++ to prevent it. A germanium or Schottky rectifier diode would be best, but in most cases a silicon rectifier is adequate. digital loads are not fed into the analog ground line. A recommended connection sequence for the ground lines is shown in Figure 16.
Application Notes
Some application notes that may be found useful are listed here:
NOTE # AN016 AN017 AN018 DESCRIPTION "Selecting A/D Converters", by Dave Fullagar "The Integrating A/D Converter", by Lee Evans "Do's and Don'ts of Applying A/D Converters," by Peter Bradshaw and Skip Osgood "Building a Battery-Operated Auto Ranging DVM with the ICL7106"
Analog and Digital Grounds
Extreme care must be taken to avoid ground loops in the layout of ICL7104 circuits, especially in 16-bit and high sensitivity circuits. It is most important that return currents from
BUFF OUT PIN 35 ICL7104 AN GND BUFF -IN (IF USED)
AN030
REF VOLTAGE VREF
EXTERNAL REFERENCE (IF USED) PIN 35 ICL7104 AN GND
+15V
-15V
+ VIN
-
I/P FILTER CAP
CAZ
8068 PIN 2 COMP
BOARD EDGE
SUPPLY RETURN
DIGITAL LOGIC
DIG GND ICL7104 PIN 2
DEVICE PIN
+5V SUPPLY BYPASS CAPACITOR(S)
FIGURE 1. GROUNDING SEQUENCE
IC L7104 - 14 IC L7104 - 16
AUTOZERO (COUNT) 24,576 - 8,193 98,304 - 32,769
INTEGRATE (FIXED COUNT) 8192 32768
DEINTEGRATE (COUNT) 0 - 16383 0 - 65535
CONVERSION T IME (IN CONTINUOUS MODE): 32,768 t O SC (7104 - 14) 131,072
t O SC (7104 - 16)
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ICL7104
ICL7104 with ICL8052/8068 Integrating A/D Converter Equations
* Oscillator CRYSTAL or RC (RC on -14 Part Only) fOSC (Typ) 200kHz fOSC = 0.45/RC (ICL7104-14 Only) COSC > 50pF and ROSC > 50K * Oscillator Period tOSC = 1/fOSC * Integration Clock Frequency fCLOCK = fOSC * Integration Period tINT = 8192 x tOSC (7104-14) tINT = 32768 x tOSC (7104-16) * 60/50Hz Rejection Criterion tINT/t60Hz or tINT/t50Hz = Integer * Optimum Integration Current IINT = 20A * Full Scale Analog Input Voltage VINFS (Typ) = 200mV to 2V = 2V REF * Integrate Resistor
( BufferG ain ) x VIN FS R I NT = -----------------------------------------------------------II NT
VIN Count = 32768 x -------------- (7104-16) V R EF
V++ = +15V V- = -15V V+ = +5V VREF 1.75V If VREF not used, float output pin. * Auto Zero Capacitor Values 0.01F < C AZ < 1F * Reference Capacitor Value * C REF = (Buffer Gain) x C AZ
* Integrate Capacitor
( tIN T ) ( I I NT ) C INT = ------------------------------VIN T
* Integrator Output Voltage
( tIN T ) ( I I NT ) VINT = ------------------------------C IN T
VINT (Typ) = 9V * Output Count
V IN Count = 8192 x -------------- (7104-14) VR EF
* Output Type: Binary Amplitude with Polarity and Overrange Bits. * Power Supply: 15V, +5V
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